U.S. Pat. No. 5,319,755 (reference 1) discloses a conventional data transmission method between integrated circuits. According to this method, as shown in FIG. 1, a transmission line 1 serving as a data bus connects input/output circuits 3 present in respective integrated circuit chips 2. The transmission line 1 transmits digital signals to transmit data between the integrated circuits 2.
This method poses an upper limit on the data transmission speed between the integrated circuits 2, and it is difficult to transmit a basic clock of several GHz or more. The problem is negligible when the basic clock frequency of a signal propagating through the transmission line 1 is equal to or smaller than several GHz. However, when the basic clock frequency becomes equal to or higher than several GHz, the signal exhibits the dispersion phenomenon owing to the property of the transmission line 1, and the influence of the dispersion phenomenon is not negligible. The dispersion phenomenon is that the pulse transmission speed changes depending on the frequency component, so input and output pulses differ in shape or the pulse width increases, inhibiting high-speed pulse transmission. This problem becomes serious when a capacity 5 accessory to the input/output circuit 3 of the integrated circuit 2 has a larger value.
U.S. Pat. No. 5,023,574 (reference 2) discloses a technique of generating a high-speed pulse. According to this technique, many varactor diodes are arranged at proper intervals in a transmission line to generate a nonlinear wave. This technique is disadvantageously applicable to only a case where the structure of a transmission line is very special, i.e., the transmission line is formed on a board surface, like a microstrip line or coplanar line, because varactor diodes must be inserted midway along the transmission line.
Japanese Patent Laid-Open No. 2001-111408 (reference 3) discloses a structure for packaging a high-speed signal transmission wire. In this structure, the distance between an impedance mismatched portion on a transmitting board and that on a receiving board is set such that the signal transmission time becomes an integer multiple of the time half the signal switching cycle. This structure suppresses temporal fluctuations caused by a reflected wave, and reduces jitters. Japanese Patent Laid-Open No. 2001-251030 (reference 4) discloses a line system between integrated circuits that controls a signal transmission delay by arranging a capacitive load structure on a line connecting integrated circuits.
Japanese Patent Laid-Open No. 2003-198215 (reference 5) discloses an arrangement which unifies the signal transmission speed. According to this reference, a long transmission line is formed in a low-permittivity region, and a short transmission line is formed in a high-permittivity region on a transmission line board on which a plurality of circuit components are mounted on a dielectric board and many transmission lines for connecting the circuit components are formed on the dielectric substrate. Japanese Patent Laid-Open No. 5-63315 (reference 6) discloses a printed wiring board on which delay pads are arranged on part of a signal line on the printed wiring board, and delay pads corresponding in number to a change of the delay time so that the control signal and data signal become in phase.
Japanese Patent Laid-Open No. 5-283824 (reference 7) discloses a circuit board configured to prevent reflection between devices having different electrode pads by coating a circuit board having a specific permittivity with a material having a different permittivity and controlling the permittivity.